ECP/INL to present at VLSI-SoC 2025 in Chile

The Ecole Centrale de Lyon/Institut des Nanotechnologies de Lyon team will present their latest paper, “Exploring Enhancements of 1T1C FeMFET Bitcell With a Versatile DTCO Methodology,” at the IFIP/IEEE 33rd VLSI-SoC Conference in Puerto Varas, Chile (12–15 October 2025).

Congratulations to Rosario Pronsato, Antoine Cauquil, Pascal Vivet, Jean Coignus, Damien Deleruyelle, Cédric Marchand, Alberto Bosio, Lioua Labrak, and Ian O’Connor for this upcoming presentation!

Read more about the conference here.

Abstract:
Non-volatile in-memory computing (iMC) has emerged as an energy-efficient paradigm well suited to AI workloads. Its implementation using 1T1C FeMFETs (Ferroelectric Memory Field Effect Transistors), a best-in-class emerging nonvolatile memory technology that integrates BEOL ferroelectric devices with FEOL transistors, is of particular interest. This interest stems from their potential to enable large-scale multiply-accumulate (MAC) operations in both digital and analog domains. However, realizing tangible performance benefits requires comprehensive cross-layer exploration of both design and technology parameters, extending up to accelerator level. In this work, we propose a bitcell-level multi-objective optimization methodology to identify and extract optimal sizing solutions that provide tractable trade-offs between key performance indicators (KPI). We further demonstrate how this approach facilitates cross-stack exploration of accelerator architectures. Results are presented as Pareto fronts spanning 2-4 KPIs: a 2-KPI problem illustrates the methodology, while a 4-KPI problem represents a realistic design scenario. Comparison is made between 130nm and 28nm technologies demonstrating a decrease in the average of write energy and area up to 24X and 30X respectively.