Highlights from the 2025 International Memory Workshop
The 17th International Memory Workshop (IMW), held from May 18–21, 2025, in scenic Monterey, California, brought together more than 200 global participants to explore cutting-edge developments in memory technologies. Organized under the auspices of the IEEE Electron Devices Society, the IMW continues to serve as a premier forum for technologists and researchers to share the latest breakthroughs in memory science and engineering.
All the major players in the memory and semiconductor industry were present (TSMC, Micron, Nvidia, SK hynix, Sony, STMicroelectronics, Infineon, and NXP, among others), underscoring the workshop’s stature as a vital event for both academic and industry stakeholders.
Focus on Advanced DRAMs and HBM for AI
This year’s tutorial sessions were particularly impactful, with a strong focus on advanced DRAM and High Bandwidth Memory (HBM) tailored for AI applications.
Gaurav Thareja of Applied Materials discussed the materials, process, and system-level co-optimization for next-generation HBM, highlighting how materials innovation plays a critical role in enabling bandwidth scaling.
From SK hynix, Han Suk Ko and Younsoo Kim delivered a forward-looking view on the challenges and opportunities for HBM in AI, emphasizing power, performance, and scaling trends.
Gautam Bhatia of NVIDIA presented insights into GPU memory design for AI workloads, spotlighting the interplay between AI acceleration and memory bandwidth needs.
NAND and Vertical Memory Breakthroughs
The “NAND II” session featured Albert Chen (SanDisk), who tackled the complexities of OpenBlock reads in 3D NAND, an increasingly important area as layer counts climb and latency becomes a bottleneck.
Another standout was Kai Ni (University of Notre Dame), who introduced a compelling tutorial on ferroelectric and vertical NAND, proposing ferroelectrics as a transformative element in the future of NAND architectures.
Ferroelectric Memory: A Rising Star
Ferroelectric memory technology made a strong showing across multiple presentations.
E. Sarkar (Georgia Tech) shared progress on Ferroelectric FinFETs, a key structure for future logic-memory integration.
Mor Dahan (Technion) demonstrated non-destructive FeRAM readouts, a long-standing goal in the ferroelectric community, earning NaMLab and his team the Best Student Presentation Award.
Tarcisius Januel (CEA/Leti) showcased hybrid RRAM/FeRAM memory achieving ferroelectric endurance of 200k cycles on a 16kbit matrix with a compact 0.24 μm² memory cell design, aligning with the OxRAM reliability data presented by Martemucci et al. at IEDM 2024.
Toward Automotive-Grade Ferroelectric Memory
In the automotive domain, Fraunhofer unveiled an Al-doped HfZrO (HZO) ferroelectric memory that meets automotive-grade standards with temperature qualification up to 175°C. This development marks a significant step toward deploying ferroelectric memory in harsh-environment applications, such as advanced driver-assistance systems (ADAS) and autonomous vehicles.