Strengthening ECL–TU Delft Collaboration on DTCO and System-Level Simulation

In mid-December 2025, Antoine Cauquil, a PhD student at ECL – École Centrale de Lyon, spent a week at TU Delft. The visit proved highly successful and productive, enabling in-depth technical discussions, alignment on next research steps, and the identification of concrete follow-up actions.

Talks centered on integrating TU Delft's system simulator work with ECL's bitcell exploration and design-technology co-optimization (DTCO) efforts. ​The immediate priority involves finalizing a cost-based model (incorporating power, area, and latency) alongside an analog array representation that accounts for parasitic process variations in current summation. 

Design-space exploration was also addressed across diverse bitcells, peripherals, interconnects, array sizes, and tiling strategies, varying parameters individually to assess overall impacts. The simulator's generic design facilitates easy adaptation to various technologies, topologies, and structures.

(Left to right) Theofilos Spyrou, Konstantinos Stavrakakis, Antoine Cauquil, Ethan Zhang, and Rajendra Bishnoi in Delft.