Breakthrough FeMFET Memory Optimization Wins Best Paper at VLSI-SoC 2025, Paving the Way for More Efficient AI Hardware

At VLSI-SoC 2025 in Puerto Varas (Chile), the Electronics group from INL received the Best Paper Award for their work "Exploring Enhancements to 1T1C FeMFET Bitcells with a Versatile DTCO Methodology".

The team introduced a powerful design–technology co-optimization (DTCO) framework that links material, device, and circuit design choices to system-level performance in ferroelectric memory-based computing. Their method enables designers to simultaneously tune competing goals like speed, energy, and area, extracting Pareto-optimal trade-offs across technology generations (from 130 nm to 28 nm) and demonstrating energy reductions of up to 24×.

This breakthrough is significant because it provides a scalable, data-driven approach for optimizing emerging non-volatile in-memory computing hardware - an essential step toward more energy-efficient and adaptive AI accelerators that exploit the physics of ferroelectric materials.